Christophe Suzor in France my personal blog, a place to speak out in public


Memory BIST analysis

Modern SOC (system on chip) include embedded memories, sometimes tens or hundreds of small memories. Testing these memories for quality involves triggering BIST (buit in self test), and collecting the result, as a pass/fail or as a list of failing adresses.

With Yield loss on the embedded memories increasing to unacceptable levels, engineers need visibility into the failures, with signature analysis to quickly estimate the failure mechanisms, and export of exact locations for physical failure analysis.

Typical failure mechanisms include design errors, voltage or power problems, patterning or related process problems, random defects, electrical variability, and others.

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